In the area of computer data processing systems, various types of digital logic circuits are used in different parts of the processing system. The various circuit types operate at different switching speeds and are used to provide optimal performance for the processing system. In order to transfer data from one part of the processing system having logic of one circuit type (e.g. emitter coupled logic (ECL)) to another part of the processing system having logic of another circuit type (e.g. complementary metal-oxide semiconductor (CMOS)), a translation is often required from one circuit type to another circuit type, because the circuit types operate with different input/output voltages corresponding to high and low logic levels.
Bipolar ECL voltage levels have a relatively small voltage swing of only about 0.8 volts. CMOS voltage levels have a larger voltage swing of about 5.0 volts. Since many of the processing systems are designed with both ECL and CMOS logic circuits, there are interface circuits required, such as ECL to CMOS translator circuits, to allow these two different types of circuits to communicate to each other. For example, ECL to CMOS translators are used to shift the voltage levels of the ECL input logic signals to voltage levels which can be recognized by the CMOS logic circuits.
The conventional translators do not provide a CMOS output that symmetrically tracks an ECL input. For example, it is desirable that the delay between the ECL signal rise and the CMOS signal rise be equal to the delay between the ECL signal fall and the CMOS signal fall. The designs of conventional ECL to CMOS translators do not provide this symmetrical tracking of the signal rise and fall. The delays between the ECL input signal transitions and the CMOS output signal transitions are often not symmetrical. For example, the fall to fall delay between the ECL input and the CMOS output may be less than the rise to rise delay between the ECL input and the CMOS output due to the difference in voltage levels required for switching between logic levels. In typical prior translators, the difference between fall to fall delay and rise to rise delay can be greater than 1 nanosecond (ns). To provide a symmetrical delay, the difference between the fall to fall delay and rise to rise delay should be 0.3 ns or less.
In addition, conventional translators are sensitive to variations in process parameters, power supply voltages, temperature and manufacturing tolerances. This sensitivity can significantly affect the symmetrical tracking of signal rise and fall.
In many applications it is not necessary that there be a symmetrical tracking of the rise and fall. However, when the ECL input signal is in the form of ECL differential input signals which are used to carry both data information and the clock frequency of a system, such as a non-return-to-zero, invert-to-one (NRZI) or data/frequency signal, the lack of symmetry in the CMOS output signal caused by the translator will result in inaccurate detection of the clock frequency.
Accordingly, there is a need in the art for a circuit that provides reduced sensitivity to variations in process parameters, power supply voltages, temperature and manufacturing tolerances. There is also a need in the art for a circuit that provides symmetrical tracking between the rise to rise and the fall to fall delays.